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Kumar Venkat's CV


  • Proven sustainability expert and thought leader.
  • Experienced engineer, software developer and project/business manager.
  • Founded two small technology firms in sustainability and electronic design, served as chief technologist and software developer in both, and directly supported numerous customers.
  • Technical expertise includes: life cycle assessment (LCA), carbon footprinting/GHG emissions, supply chains, resource efficiency, waste reduction, computer modeling, simulation, and analytics.
  • Master's degree in electrical and computer engineering. Graduate certificate in computer modeling and simulation.
  • Extensive research, technical and freelance publications, and two engineering patents.


  • 12/07 - present: President & Chief Technologist, CleanMetrics Corp., Portland, OR
    • Providing environmental performance and sustainability solutions to customers in diverse economic sectors. Served nearly three dozen customers to-date. (Company overview, products, solutions and customers.)
    • Solutions include software tools (ASP.NET web apps written in C#) and consulting for: life cycle assessment (LCA), carbon footprinting, GHG emissions inventories, supply-chain/value-chain analysis including scope 3 emissions, water footprinting, resource efficiency, and waste reduction.
    • Software tool innovations include:
  • 09/95 – 12/07: President & Chief Technologist, Surya Technologies, Inc., Cupertino, CA & Portland, OR
    • Provided electronic design automation (EDA) software for modeling, analysis, simulation, optimization and verification of large integrated circuit designs.
    • Software tools and technologies delivered to customers include: timing analyzer, design rules/constraints verifier, signal coupling and noise analyzer, timing optimizer, and timing-driven design partitioner.
    • Programming languages and platforms used for software development: C, C++, Yacc, Lex, Perl, UNIX, Linux.
    • Key customers in the US, Japan and India: Advanced Micro Devices, Equator Technologies, C-Cube Microsystems, Seiko Instruments, 3Dfx Interactive, Fujitsu Microelectronics, CadMOS Design Technology (now part of Cadence), Procket Networks,  ReShape, SII EDA Technologies, Atrenta, and JEDAT Innovation.
  • 06/91 - 8/95: Member of Technical Staff & Project Leader, Silicon Graphics, Mountain View, CA
    • Led a software R&D team in the development of a new gate-and-transistor-level static timing verifier that includes a number of innovative features. Developed detailed timing models for electronic circuits at the transistor and gate levels. Directed and participated in a 2-year software development project. This tool has been used to analyze/verify large standard-cell and custom integrated circuit designs.
    • Led a hardware design team in the development of a high-bandwidth memory subsystem for SGI's Challenge multiprocessor server systems. Responsible for two large ASICs and complex system design. Also, developed CAD methodology and tools to support/enhance testability, timing analysis and design rule checking. Received a US patent for part of this work.
  • 06/89 - 06/91: Member of Technical Staff, Sun Microsystems, Mountain View, CA
    • Designed a secondary cache-controller chip for Sun's SuperSparc microprocessor. Also, designed the scan/JTAG test logic for the chip. Contributed to CAD methodology including timing analysis, synthesis and circuit verification. Received a US patent for part of this work.
  • 03/88 - 06/89: Senior Design Engineer, Intel Corp., Santa Clara, CA
    • Member of the 486 microprocessor design team. Responsible for processor architecture issues, microcode development, architecture/microcode verification, and verification tools.
  • 03/85 - 03/88: Systems Engineer, Reflectone Inc., Tampa, FL
  • 06/84 - 02/85: Design Engineer, Dynamic Computer Architecture, St. Petersburg, FL


  • 1/05 – 3/06: Portland State University, Portland, OR
    • Graduate Certificate in Computer Modeling and Simulation. Focus: System dynamics, discrete-event simulation, agent-based simulation, optimization, and statistical analysis. Used software tools such as Vensim, Arena, NetLogo, and MATLAB. GPA: 4.0.
  • 1/99 – 12/99: University of California, Berkeley, CA
    • Undergraduate and graduate courses in the natural sciences. Focus: Biology, biochemistry and ecology. Grades: A's.
  • 9/88 – 3/90: Stanford University, Stanford, CA
    • Graduate courses in electrical/computer engineering. Focus: VLSI design and parallel computer architectures. Grades: A's.
  • 8/85 – 12/87: University of South Florida, Tampa, FL
    • Graduate courses in electrical engineering. Focus: Digital communication systems and digital signal processing. GPA: 4.0.
  • 1/83 – 8/84: University of Texas, El Paso, TX
  • 7/77 – 5/82: University of Madras, India
    • BS in Electrical Engineering. Senior project: Stability Analysis of Electric Grids. Grade: Honors.


Recent Press & Interviews


  • US patent # 5,987,570:“Performing overlapping burst memory accesses and interleaved memory accesses on cache misses”, Nov. 16, 1999.
  • US patent # 5,272,664:“A high memory capacity DRAM SIMM”, Dec. 21, 1993.

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